1. Field of the Invention
The present invention relates to the formation of metal interconnects on semiconductor wafers. More particularly, the present invention relates to the formation of low resistance damascene copper interconnects.
2. Description of the Related Art
As integrated circuit devices grow smaller and smaller, higher conductance and lower capacitance is required of the interconnecting wires (i.e., interconnects). In order to accommodate these objectives, the trend has been towards the use of copper for interconnects and damascene methods for forming the interconnects. One drawback to the use of copper in the interconnects is its tendency to diffuse (i.e., leakage) into adjacent dielectric layers. Copper diffuses easily into dielectric layers and diminishes the electrical insulation qualities of the dielectric.
Copper diffusion barrier layers, for example layers containing tantalum, have been deposited before the deposition of copper to prevent “leakage”. This barrier layer must be able to prevent diffusion, exhibit low film resistivity, have good adhesion to dielectric and Cu and must also be compatible with chemical mechanical polishing processes. Also the layer must be conformal and continuous to fully encapsulate Cu lines with as thin a layer as possible. Due to the higher resistivity of the diffusion barrier materials, the thickness should be minimized for Cu to occupy the maximum cross-sectional area.
In the copper/low-k damascene process for backend interconnect fabrication, TaN (or TiN) is typically used as a copper diffusion barrier to prevent copper diffusion into the Inter-Metal Dielectric (IMD) layer. TaN has a much higher resistivity compared to Cu (˜250 μohms/square and <2 μohms/square for TaN and Cu respectively). Even with shrinking feature sizes, a minimal thickness of the metallic copper diffusion barrier is required to prevent diffusion of the copper into the surrounding dielectric regions. Hence, as the geometry of the via and trench size continue to shrink, the fraction of TaN resistance to the overall resistance increases. This is especially a matter of concern for the formation of vias as the resistance of the copper diffusion barrier layer contributes a large fraction of the overall resistance due to the smaller cross section of the via as compared to the trenches. This causes undesirable via and metal line resistance increases. Moreover, the interface between the TaN and Cu at the bottom and top of via structures is a weak point in Electromigration (EM) defect testing.
Failures due to electromigration are a major reliability concern for the use of copper in forming interconnects. Electromigration is the current induced diffusion of atoms due to the momentum transfer from moving atoms. Electromigration may result in voiding and thus open circuit failures. When these voids coincide with the interfaces at the top and bottom of the vias with surrounding interconnect lines, for example between the vias and bottom metal interface, the via connection fails or becomes highly resistive. The presence of thick copper diffusion barrier layers adds to this failure process by increasing current crowding and stress, and reducing critical void volume needed to cause via open.
Accordingly, what is needed is an improved process for forming damascene copper wiring in such a manner so as to minimize overall via and metal line resistance increases.